FPGA-Based Bilinear Interpolation Image Scaler with Q8 Fixed-Point Arithmetic and Hardware-Software Co-Verification
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Keywords
FPGA, bilinear interpolation, image scaling, fixed-point arithmetic, line buffer
Abstract
Image scaling serves as a critical performance bottleneck in real-time video pipelines powering multi-resolution embedded display systems. The design integrates a dual ping-pong line buffer architecture to deliver four pixels per clock cycle, paired with a digital differential analyzer (DDA) for precise sub-pixel coordinate generation. A four-stage pipelined interpolation core optimized for Xilinx Digital Signal Processing 48 (DSP48) slices achieves one-pixel-per-cycle throughput with only six cycles of end-to-end latency. Hardware-software co-verification conducted on ModelSim SE-64 demonstrates perfect reconstruction of constant-color images and 25.8 dB Peak Signal-to-Noise Ratio (PSNR) for gradient images at 4x4 identity scaling. Resource estimates for a Xilinx Artix-7 XC7A35T indicate the design occupies merely 3.8% of available Look-Up Tables (LUTs) and 6.7% of DSP48 slices, making it exceptionally suitable for low-power embedded applications.
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