Hybrid and Time/Frequency-Domain Approaches for Low-Power High-Performance ADCs/DACs: Recent Advances and Perspectives
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Keywords
ADC/DAC, low-power, high-performance, hybrid architecture, time/frequency domain
Abstract
The continuous advancement of modern communication systems and sensing technologies has urgently demanded low -power, high -performance Analog -to-Digital Converters (ADCs) and Digital -to-Analog Converters (DACs). To address this need, this paper presents a s ystematic review of current optimization strategies, employing literature analysis and architectural comparison to evaluate approaches that aim to balance power efficiency and performance while highlighting their limitations. This review concludes that hybrid architectures and time/frequency -domain methods offer novel perspectives for achieving low -power and high -performance ADC/DACs, with NS -SAR ADCs and TDC -based ADCs identified as particularly promising candidates. Despite numerous proposals to mitigate noise, complete solutions have yet to be realized. Analysis using the Schreier Figure of Merit ( FoM) further confirms that high performance and low power consumption remain inherently conflicting objectives. While existing methods have achieved significant improvements in either power efficiency or performance, the development of an ADC/DAC that simultaneously optimizes both metrics remains an open challenge. The insights presented in this review are expected to guide future research on the design of energy -efficient data converters, ultimately supporting the advancement of communication systems, sensors, and other electronic technologies, and contributing to more intelligent and convenient applications in modern society.
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