Optimization of Lithography Process Parameters for Improving Photodetector Array Performance
Main Article Content
Keywords
photodetector array, lithography process, exposure dose, line width uniformity, alignment accuracy
Abstract
Photodetectors are widely used in environmental monitoring, optical communication, industrial inspection, and imaging systems. As photodetector devices advance toward higher resolution, smaller pixel sizes, and larger array integration, lithography has bec ome a key fabrication process that affects electrode accuracy, active-region geometry, and device consistency. This paper investigates the influence of lithography process parameters on the fabrication quality and photoelectric performance of photodetector arrays. Focusing on silicon-based and InP substrates, the study analyzes the effects of exposure dose, development time, baking temperature, and alignment accuracy on line width uniformity, electrode spacing, dark current, responsivity, and array yield. The results show that optimized step-and-repeat lithography can effectively reduce line width deviation, improve multilayer alignment accuracy, and enhance device uniformity. In particular, an appropriate exposure dose helps maintain well-defined photoresist patterns, reduce edge distortion, and improve electrode consistency. These process improvements contribute to lower dark current, higher responsivity, and improved production yield in array photodetectors. This stud y demonstrates that systematic lithography parameter optimization can enhance photodetector performance without introducing major changes to existing fabrication equipment, providing a practical process reference for small - and medium -scale optoelectronic device manufacturing.
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