A Review of the Applications of Artificial Intelligence in the Full-Process Design of Integrated Circuits
Main Article Content
Keywords
artificial intelligence, integrated circuit design, EDA, large language model, reinforcement learning, graph neural network
Abstract
In the post-Moore era, traditional integrated circuit (IC) design faces bottlenecks such as long design cycles, high costs, and difficulty in PPA convergence. Artificial intelligence (AI), with its data-driven and global optimization capabilities, has pene trated the entire IC design process. This paper systematically reviews the technological evolution of AI in full-process IC design, with emphasis on algorithmic representation mechanisms—from how Graph Neural Networks (GNNs) model congestion as node and edge features, to how Circuit Transformers capture long-range dependencies in directed acyclic graphs. We also analyze engineering practices of AI -EDA integration in industry and discuss technical challenges, including generalization, interpretability, and physical consistency, providing a reference for related research.
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